Aimed at the problems that the performance of laser modulator with high power chips in optical modules becomes deteriorated, and bit error rate caused by the clock reference deviation between transceivers is high, a low power and high jitter tolerance clock and data recovery circuit (CDR) is proposed in this paper. By adopting a technology of voltage controlled oscillator (VCO) type and full speed CDR system architecture, and using a technology of an inductance peaking in clock buffer, the power consumption of the CDR chip is reduced. By introducing a zero point compensation resistor in the CDR integration path, the jitter tolerance of the CDR is improved. The CDR is designed with CMOS 65 nm process and supplied with 1.1 V. The back end simulation results show that when the CDR circuit works at 28 Gbps, the power consumption is 2.18 pJ/bit. When the frequency difference of the transceiver is 5 000 ppm, the jitter peak to peak value of the recovered clock is 5.6 ps, and the jitter tolerance meets the needs of design index and the CIE25/28G protocol specification.