This paper designs a fast locking and low jitter clock and data recovery circuit applied to 28 Gb/s nonreturntozero code highspeed serial optical communication receiver. In order to solve the problem that clock jitter and locking time are difficult to be considered at the same time, the lock detection and discrimination technology is proposed in the circuit with separate proportionalintegral path to realize the adjustable gain of proportional path and enable the loop to lock quickly under condition of low jitter. The simulation is carried out by Cadence Spectre. When the lock detection and discrimination technology is used in the loop, the locking time is about 400 ns and the jitter peaktopeak value is about 2.5 ps. Compared with the other two schemes, the locking time is reduced by 33% and the jitter is reduced by 43%.