The optimization design of VHDL is for the purpose of making full use of hardware resources provided by CPLD, making the item design suit to certain scale of CPLD chip, increasing the system speed and lowering the power-waste. The intention of optimization is to reduce adapted macrocell numbers, especially the GLE chip numbers of Lattice company. The fact shows that some optimization methods are effective in practice, such as changing the module structure and the method of description, making the module resources shared as much as possible, the versatility design of time-sequence electro-circuit working pattern and the selection of Flip-Flop types, etc. They can improve adaptation result of item and function price ratio to system, VHDL has great value in the exploitation and appliance of CPLD chips.